HCMC | Design & Verification Engineer

Company Profile

Client : Japanese IT company

Work Location : Dist 3, HCMC, Remote Work

Position Information

Position : Design & Verification Engineer Full-time

Position Level :Senior

Job Description

Input the specifications requested by the customer, and carry out specific design verification

work using the following languages.

  • Function specifications (English)
  • Mounting specifications (English)
  • RTL (Verilog/SystemVerilog) or high-level synthesis (SystemC/C/C++)
  • Verification strategy (English)
  • Verification item table (English)
  • Verification environment construction/verification scenario (SystemVerilog/SVA/UVM/C)
  • Verification environment manual (English)
  • Verification result report (English)

Requirement

Gender :Doesn’t matter

Age :25~40

Education :None

Language :English – Intermediate Level

<Must>

  • +3 years experience for same position
  • Skill for Verilog

<Prefer>

  • Skill for System Verilog
  • Skill for Synopsys or Cadence

Salary

Negotiable

Senior level: 30,000,000 VND~47,000,000 VND

Leader level: 47,000,000~75,000,000 VND

Benefits

  • Raise in salary (April)
  • Bonus 3 times (Summer, Winter, Tet bonus) 3 months bonus
  • Position allowance
  • IT Admin allowance(1,500,000VND/month)
  • Lunch allowance(1,000,000VND/month)
  • Work day :8:30~17:30 (Monday – Friday)
  • Holidays :Saturday, Sunday, National Holiday

Memo

If manager accept, staff can start to work remotely.

Interview Process

  • Interviewer :VN and JP manager
  • 2 round interview

Thông tin liên hệ

SAIYOLINK

Địa chỉ : Số 20, Đường số 8, KDC CityLand Park Hills Phường 10, Quận Gò Vấp, Thành phố Hồ Chí Minh.

Số điện thoại: 0968104110

Email: info@saiyolink.com

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